1. Technical Field
The present invention relates to a semiconductor device including a laminate of a plurality of semiconductor substrates connected by wires provided between the substrates and a method for producing the semiconductor device.
2. Related Art
In order to meet demands for miniaturization and weight reduction of electronic apparatuses, packaging technologies for semiconductor devices mounted in the electronic apparatuses employ a so-called surface-mounting method. In this method, semiconductor chips are mounted on a surface of a mounting substrate to reduce a size of the semiconductor devices. Among the technologies, in a chip scale packaging (CSP) technology, particularly in a wafer-level chip-scale packaging, a resin seal layer is directly formed on a surface of each semiconductor chip included in a wafer, and then, the semiconductor chips checked in that condition are cut out from the wafer and used in electronic apparatuses. Accordingly, a mounting area for a semiconductor device can be made equal to an area for the semiconductor chips, thereby obtaining a micro-miniature package.
Meanwhile, in the above-described semiconductor devices, higher performance is also demanded in addition to the demand for miniaturization. To satisfy those demands, JP-A-2004-281539 proposes a semiconductor device. The semiconductor device includes a plurality of semiconductor chips mounted in a single package to exhibit higher performance. Additionally, the semiconductor chips are mutually laminated by sandwiching an insulation layer and the like between the chips to reduce the size of the semiconductor device.
Along with the demands for further miniaturization and higher performance in semiconductor devices as described above, simplification of methods for producing semiconductor devices has also been demanded in recent years. FIG. 11 is a front view showing a front structure of a semiconductor device produced by an inkjet method as an example of the production method.
As shown in FIG. 11, on a mounting substrate 70 used for the semiconductor device, a plurality of semiconductor chips 71 having a same size are laminated in a stepped shape. Specifically, when viewed from an upper side as a normal direction of a mounting surface, the semiconductor chips 71 are sequentially laminated one on another in such a manner that upper semiconductor chips 71 avoid connection electrode pads P of lower semiconductor chips 71 and are deviated from the lower semiconductor chips 71 in a single direction on the mounting surface. Additionally, on the connection electrode pads P of each semiconductor chip 71, a linear wire 76 is laminated via an inclined portion 75 connecting the connection electrode pads P of the each semiconductor chip 71 to the substrate terminals BP of the mounting substrate 70.
In the lamination structure above, the connection electrode pads P of the each semiconductor chip 71 and the substrate terminals BP of the mounting substrate 70 can be arranged in the single direction when viewed from the upper side. Accordingly, in a process of producing the semiconductor device thus formed, liquid droplets of conductive ink are discharged in a manner so as to connect the connection electrode pads P to the substrate terminals BP, and then, the discharged ink is dried and fired. Thereby, the semiconductor device can be produced in the extremely simple process. Furthermore, connections between the respective semiconductor chips and the mounting substrate 70 can be formed by a metal film provided along an end face of each conductor chip. Thus, the semiconductor device can be further miniaturized as compared to semiconductor devices using wire bonding connections.
In the method described above, however, the connection electrode pads P of the each semiconductor chip 71 need to be arranged in the single direction when viewed from the upper side. Accordingly, arrangement positions of upper semiconductor chips 71 are more deviated in the single direction than in lower chips 71. Therefore, as a total number of the semiconductor chips 71 laminated is increased to satisfy the demand for higher performance, an area occupied by the laminated semiconductor chips 71 is extended in the single direction. As a result, the above method cannot be employed for electronic devices and apparatuses produced in standardized sizes, particularly, for electronic devices such as SD memory cards and micro SD memory cards.
Furthermore, when laminating the semiconductor chips, the upper semiconductor chips 71 may be laminated along the normal direction of the mounting surface, without being deviated in the planar direction of the mounting surface as described above. However, in the structure, the connection electrode pads P of the lower semiconductor chips 71 are covered by the upper semiconductor chips 71. Thus, it is necessary to form a wiring through-hole in each of the upper semiconductor chips 71, resulting that the production process becomes complicated, and furthermore, checking of the each semiconductor chips becomes difficult.